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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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autowire creates wrong width definition #1712

Closed jlechnar closed 3 years ago

jlechnar commented 3 years ago

Hello,

in the following code the automatic wire contains a wrong width definition. See ISSUE. (fyi. This worked in a previous version from ~1-2years, found after updating to the latest code here). Please also find attached a minimum example.

BR, Joachim

parameter_auto_wire.tar.gz

   parameter WIDTH = 16;

   // ISSUE: in autowire below [WIDTH*0-1:0] should have been [WIDTH*2/8-1:0]

   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [WIDTH*0-1:0]   signal;                 // From subtestout of subtestout.v
   // End of automatics

   subtestin #(.WIDTH(WIDTH)) subtestin
     (/*AUTOINST*/
      // Inputs
      .signal                           (signal[WIDTH*2/8-1:0]));
wsnyder commented 3 years ago

Thanks for the good report. As you probably guessed it was assuming X/Y had no remainder, so 2/8=0. Fixed.

jlechnar commented 3 years ago

You are welcome. Thanks for fixing!