indent issue after double comment or comment in input signal line ?

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

http://veripool.org/verilog-mode

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indent issue after double comment or comment in input signal line ? #1717

Closed jlechnar closed 2 years ago

jlechnar commented 3 years ago

Hello,

In the following code test1 is indented wrong. It seems wire is aligned to test3 from before. I am using the latest verilog-mode version.

module test
  (input wire test5 // bla
   /*AUTOARG*/);

`include "bla.vh"

   reg        test4;

   wire       test3;

   //  // FIXXME
              wire       test1 = test2; // wrong indent
   wire                  test = test;

endmodule

Sorry I could not break it down further.

BR, Joachim

wsnyder commented 3 years ago

Looks like verilog-continued-line-1 is not handling this. Needs more debug if you or someone gets a chance.

gmlarumbe commented 2 years ago

Hi,

Commit 4730c15 fixes the issue with GNU Emacs 28.1.

Can you test if everything still works fine with this patch before merging into master?

Thanks!