AUTOINST with packed array of typedef's breaks

[sjalloq]

I'm opening this after finding an old issue that matches, #1485. I've got the same issue and your suggestion of adding the regex hint works for a simple test case but not for our main RTL.

The testcase I've got is:

typedef logic unsigned vector_t;

module test (
  output vector_t car_o,
  output vector_t [1:0] vec_o
);

endmodule

module top ();

  output vector_t       car_o;
  output vector_t [1:0] vec_o;

  test u_test (/*AUTOINST*/
               // Outputs
               .car_o                   (car_o),
               .vec_o                   (vec_o[1:0]));

endmodule

// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:

but in our real RTL I effectively have the following snippets in a larger module. Any thoughts on what could be wrong?

typedef      logic unsigned     [AFE_NUMBER_CHANNELS-1:0]         afe_channel_vector_t;

module child_module (
  output afe_channel_vector_t     [1:0]                         afe_sc_o
);
//blah
endmodule

module parent_module();
  child_module u_child (/*AUTOINST*/);
           .afe_channel_vector_t        (afe_channel_vector_t/*.[1:0]*/),
           .afe_sc_o                    (afe_sc_o),
);
//blah
endmodule

// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:

[sjalloq]

D'oh! You have to define the verilog-typedef-regexp in the child module.