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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Avoid leaving extra spaces before tabs on lining up declarations #1723

Closed t-a-k closed 3 years ago

t-a-k commented 3 years ago

I have found that verilog-pretty-declarations and verilog-indent-declaration leave extra (redundant) space when indent-tabs-mode is non-nil.

For example, applying verilog-pretty-declarations on the following code will indent the third line to logic<SP><TAB>b;, but I think <SP> is redundant in this case.

module test;
   logic [31:0] a;
   logic b;

This PR attempts to fix this.

wsnyder commented 3 years ago

Thanks for looking into and fixing this, looked great.