search

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
247 stars 90 forks source link

Match only alphabet in cell name #1726

Closed imgod2u closed 3 years ago

imgod2u commented 3 years ago

I'm trying the following template:

.\(.*\) (@"(verilog-string-replace-matches \\"^\\\\([a-z]*\\\\)_\\\\w*$\\" \\"\\\\1\\" nil nil (downcase vl-cell-name))"_\1),

I want to prepend the first alphabetic sequence ("pdd" in "pdd_inst") to each signal name.

However, the string [a-z] doesn't seem to match and my signal always ends up:

"cell-name"_sig

Any help with the syntax here would be greatly appreciated. I've tried a few variants:

.\(.*\) (@"(verilog-string-replace-matches \\"^\\\\(\\\\[a-z\\\\]*\\\\)_\\\\w*$\\" \\"\\\\1\\" nil nil (downcase vl-cell-name))"_\1),
.\(.*\) (@"(verilog-string-replace-matches \\"^\\\\(\\\\[a-z\\\\]\\\\+\\\\)_\\\\w*$\\" \\"\\\\1\\" nil nil (downcase vl-cell-name))"_\1),

With no success.

wsnyder commented 3 years ago

Don't escape the brackets, only parenthesis. Also I would avoid using the \w escape, use e.g. [a-zA-Z0-9_]

imgod2u commented 3 years ago

Thanks a lot! That worked.