parameters that exist in a package are treated like input signals

[imgod2u]

I have the following code:

my_pkg.sv:

package my_pkg;
  parameter PARAM1 = 4;
endpackage

my_top.sv:

module my_top import my_pkg::*;
(
  input clk,
  input rst_n,
  /*AUTOINPUT*/
);

logic [PARAM1-1:0] sig1;

my_mod0 u_mod0(
  .output_port0(sig1[PARAM1-1:0],
  ...
);

my_mod1 u_mod1(
  .input_port0(sig1[PARAM1-1:0],
  ...
);
endmodule

The issue is when run verilog-auto on this, I get something like:

module my_top import my_pkg::*;
(
  input clk,
  input rst_n,
  /*AUTOINPUT*/
  // Beginning of automatic inputs (from unused autoinst inputs)
  input logic          PARAM1,           // To u_mod1 of my_mod1.sv
  ...
);

logic [PARAM1-1:0] sig1;

my_mod0 u_mod0(
  .output_port0(sig1[PARAM1-1:0],
  ...
);

my_mod1 u_mod1(
  .input_port0(sig1[PARAM1-1:0],
  ...
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-flags: ("-f filelist.f")
// verilog-auto-wire-type:"logic"
// verilog-typedef-regexp: "_t$"
// End:

It seems it's unable to recognize that the PARAM1 parameter comes from a package....

My filelist.f:

my_pkg.sv
-v my_mod0.sv
-v my_mod1.sv
my_top.sv

Is this expected?

[wsnyder]

Unfortunately verilog-mode doesn't process imports. It's unlikely this will get improved as its difficult. If you want to work around this you'll need to use my_pkg::PARAM1 instead.