Closed afuller525 closed 2 years ago
I don't see the AUTOWIRE declaring mystruct_t. Are you sure you are using the most recent version of verilog-mode?
I apologize, it looks like my company is using a very old version (840). I tested a local override with the newest version and the problem is resolved.
Thanks.
I am attempting to use user-defined struct objects on the port list of a submodule. I discovered that /AUTOWIRE/ is failing to notice if an intermediate bus is already defined if it is of a user-defined type. This leads to the bus being added to the automatic wire list unnecessarily, and then the compiler gives a redeclaration error.
Below is a very contrived and simplified example. In the top module, the object "b" gets added to the automatic wires list even though it is already declared in this module scope.
<<>>
module top (c, a);
endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End:
<<>>
module submod (out, in); typedef struct { logic x; logic y; } mystruct_t;
endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End:
Thanks for your help.