I use a bunch of filelists to tell Verilog-Auto how to expand my various design files. However, I have some 3rd party IP (which come with a filelist) that I want to include in my design.
My go-to so far has been to just include their filelists in my filelist using -f.
However, it seems some of their files are pretty big (TIE.v is pretty big for example).
Two questions:
Is there a way to disable this prompt? I'm using batch mode in a Makefile and would like it to run through
Is there a way to exclude certain files when Verilog-Auto reads the filelists? Maybe by filename?
I use a bunch of filelists to tell Verilog-Auto how to expand my various design files. However, I have some 3rd party IP (which come with a filelist) that I want to include in my design.
My go-to so far has been to just include their filelists in my filelist using -f.
However, it seems some of their files are pretty big (TIE.v is pretty big for example).
Two questions: