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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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it's possible to keep the order of input and output port when auto inst? #1745

Closed zhanjf closed 2 years ago

zhanjf commented 2 years ago

hi, it's possible to keep the order of port when auto inst like the following example, keep the input and output order?
Thanks!

DWC_mipi_dsi_host i_DWC_mipi_dsi_host_left (/AUTOINST/ //APB Interface .presetn (presetn ), // input .pclk (pclk ), // input .paddr (paddr[9:0] ), // input .penable (penable ), // input .psel (psel ), // input .pwrite (pwrite ), // input .pwdata (pwdata[31:0] ), // input .prdata (prdata[31:0] ), // output .interrupt (interrupt ), // output //DPI INTERFACE .dpipclk (dpipclk ), // input .dpivsync (dpivsync ), // input .dpihsync (dpihsync ), // input .dpipixdata (dpipixdata[`DSI_HOST_PIXELDATAWIDTH-1:0] ), // input .dpidataen (dpidataen ), // input .dpishutdn (dpishutdn ), // input .dpicolorm (dpicolorm ), // input .dpiupdatecfg (dpiupdatecfg ), // input .edpihalt (edpihalt ), // output

wsnyder commented 2 years ago

No, because the // Input and // Output comments are "magic" so they need to be in that order. Sorry.