veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

http://veripool.org/verilog-mode

GNU General Public License v3.0

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Does verilator support the parameter integer array? #1746

Closed shawn110285 closed 2 years ago

shawn110285 commented 2 years ago

module tilelink_master2slave_a_channel

(parameter NUM_MASTER = 3, ADDR_WIDTH =32, DATA_WIDTH=32, SRC_ID_WIDTH = 3, SIZE_WIDTH = 2, parameter integer MASTER_ID_BASE[NUM_MASTER-1:0]={2,1,0},

        ADDR_Low  =32'h00000000,
        ADDR_High =32'h00000fff

) ( input logic clk_i, input logic rst_n_i, ... );

verilator reported the error as below: Unsupported: Replication to form 'integer$[2:0]' data type

wsnyder commented 2 years ago

This has nothing to do with Verilog-Mode. Please use Verilator https://github.com/verilator/verilator/ instead. However to answer, use a pattern assignment ";{".