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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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the support to parameter integer array #1747

Closed shawn110285 closed 2 years ago

shawn110285 commented 2 years ago

module tilelink_matrix

(parameter NUM_MASTER = 3, NUM_SLAVE = 6, ADDR_WIDTH =32, DATA_WIDTH=32, SRC_ID_WIDTH = 3,SIZE_WIDTH = 2, SINK_ID_WIDTH =3,

//--------------debug----//---CLIC----//periph port// sys port // TIM0 // TIM1
parameter integer ADDR_Low[0:NUM_SLAVE-1] = {32'h00000000, 32'h02000000, 32'h20000000, 32'h40000000, 32'h80000000, 32'h80008000}, //address high is upper boundary address +1; parameter integer ADDR_High[0:NUM_SLAVE-1] = {32'h00001000, 32'h03000000, 32'h30000000, 32'h50000000, 32'h80008000, 32'h80010000} ) ( input logic clk_i, input logic rst_n_i, ... )

verilator reported the warning as following: Operator VAR 'ADDR_Low' expects 32 bits on the Initial value, but Initial value's CONST '192'h200000020000000400000008000000080010000' generates 192 bits.

wsnyder commented 2 years ago

This has nothing to do with Verilog-Mode. Please use Verilator https://github.com/verilator/verilator/ instead. However to answer, use a pattern assignment ";{".