AUTOINPUT can not create signal with nettype

[kopinions]

Code snippet like below /*AUTOINPUT*/

generated like below

input a;
input [7:0] b;

the setting is below

verilog-auto-declare-nettype="wire"
verilog-auto-wire-type="wire"

after some investgation, it seems that when I set the auto-wire-type, the declare nettype is not work

[wsnyder]

verilog-auto-wire-type is only for AUTOLOGIC/AUTOWIRE. verilog-auto-declare-nettype should work though, see this example: https://github.com/veripool/verilog-mode/blob/master/tests/autoinput_none.v