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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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fix: should able to declare the input as wire #1755

Closed kopinions closed 1 year ago

kopinions commented 2 years ago

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wsnyder commented 2 years ago

Thanks for looking into the code and making a pull request!

In general to accept a patch I'll need the patch to include a test/{something}.v for the new case (unless an existing one covers it), and appropriate test_ok/something.v file that shows the correct output result. A "HARNESS_UPDATE_GOLDEN=1 make test" can generate the test_ok files.

As to the specific patch, the comment right above what you inserted indicates why that might not be what you want:

   ;; Want "type x" or "output type x", not "wire type x"
kopinions commented 2 years ago

How can I get the 

input wire [7:0] xx

from 

/*AUTOINPUT*/

while the verilog-auto-wire-type is "wire", and the verilog-auto-declare-nettype is "wire"? It seems that this case is not covered, is this intentional?

wsnyder commented 2 years ago

I think your patch would only insert that for "input". Right now it's also doing it for output. Not sure which way inout should go.

wsnyder commented 2 years ago

Never heard back about this pull request, if you'd like it merged please update per the feedback, otherwise I'll just close it out, thanks.