Closed thfirst closed 2 years ago
Fixed some typo: module Test (/AUTOARGS/); parameter FOR_NUMS = 8; @for i = 0 to FOR_NUMS // it is illegal for now__ input [31:0] P@i@ ; @endfor
Is there any work-around solution ?
There's intentionally no "for" loops in verilog-mode.
Although note you could use AUTOINSERTLISP to write your own for loop or otherwise do anything that generates code.
I see. Thanks a lot.
Thanks for taking the time to report this.
Can you attach an example that shows the issue? (You may want to attach output from 'M-x verilog-submit-bug-report')
Can you please check your github name is set to your real name (click on your avatar icon in upper right, then "settings" then "Name")?
I hope to use the defined "parameter" as the loop constant in the RTL as following:
module Test (/AUTOARGS/); parameter FOR_NUMS = 8; @for i = 0 to FOR_NUMS //it is illegal for now input [31:0] P@i@ ; @endfor
Is there any work-around solution ?