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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Symbol's value as variable is void #1759

Closed futurehome closed 2 years ago

futurehome commented 2 years ago

I try to use the following template to convert part of the port name to lowercase, it gives the error: "Symbol's value as variable is void", the \1 has been replaced by the matched part in the port name, but seems it's been treated as variable, not string. Why?

.DFT_(.*) (@"(downcase \1)"[]),

wsnyder commented 2 years ago

There's an example on the FAQ: https://github.com/veripool/verilog-mode/blob/master/FAQ.rst#how-do-i-use-auto-template-to-lower-case-all-signals

But to answer your question you need to quote and escape the \1

          .DFT_\(.*\) (@"(downcase \\"\1\\")"[]),
futurehome commented 2 years ago

Great thanks. It works.