Closed sjalloq closed 2 years ago
Verilog-mode intentionally allows
submod `mydefine"
and ` ifdef is equivalent to a define as far as this goes as Verilog-mode otherwise ignores ifdefs. So this is unlikely to ever get fixed, but thanks for reporting as it might help others out.
I suspect putting the ifdef inside the #( will fix it.
OK, understood and thanks for the fast response.
I've just been setting up a flow to run all our code through
verilog-batch-auto-diff
and have found some syntax that verilog-mode doesn't like. The following testcase shows the code:And the output from running
The code in question is pretty horrific so we will likely rewrite it anyway but wanted to report it.