Fix indentation if verilog-indent-lists is nil

[gmlarumbe]

This PR implements the indentation suggested in #1703 by setting verilog-indent-lists to nil.

Currently, if setting verilog-indent-lists to nil there are some indentation issues:

module foo # (
parameter A = 0,
parameter B = 0,
parameter C = 0
)(
input wire a,
input wire b,
output reg z
);
endmodule

gets indentend to:

module foo # (
    parameter A = 0,
          parameter B = 0,
            parameter C = 0
                  )(
    input wire a,
                  input wire b,
                  output reg z
                  );
endmodule

The patch also takes into account indentation inside generate blocks and function/tasks arguments.

[bluewww]

Seems to work well. One comment I have is that your indent_list_nil_generate_for2.v has one module statement and two endmodule statements.

[gmlarumbe]

That was some copy/paste error. Thanks for pointing out.

Updated in 6b8a328

[wsnyder]

Thanks again for fixing an issue, appreciate your getting some of these cleaned up.