Fix alignment of first port declaration

[gmlarumbe]

This PR fixes #1167

It also changes the alignment of some variables on the following tests:

• autoinst_ams_vorwerk.v
• autoinst_protected.v
• autooutput_regexp.v
• autoreset_regin.v
• autosense_gifford.v
• autosense_venkataramanan_begin.v
• indent_directives.v
• indent_replicate.v
• params_multiline_msg618.v

To me it seems better alignment but there could be something I am missing about those tests.

Another thing is the mixture of tabs/spaces in the function verilog-pretty-declarations. Would it be a good idea to untabify it in a separate commit?

Cheers!

[gmlarumbe]

Thanks @wsnyder. I really appreciate it :)