Wrong alignment of custom type ports

[gmlarumbe]

Considering the following snippet:

module foo (input logic [7:0] in1,
input logic in2,
custom_type type1,
output logic out,
custom_type type2
);
endmodule

It aligns wrongly after applying verilog-pretty-declarations:

module foo (input logic [7:0] in1,
        input logic       in2,
                  custom_type type1,
        output logic      out,
                  custom_type type2
);

The commit 91b5f59 has a workaround that prevents these custom types (word + whitespace + word) from getting aligned.

@wsnyder is it fine if I merge it? Would this be the expected behaviour?

Thanks!

[wsnyder]

Seems and improvement, go for it.