Customize indentation for multi-line parameter lines

[bjourne]

Verilog-mode lines up parameters to the opening parenthesis of multi-line parameter lists:

module counter (clk, 
                rst, 
                en, 
                out
                );

Can this feature be disabled/customized? I want to leave the first line empty and have verilog-mode indent the parameters like this:

module counter (
    clk, 
    rst, 
    en, 
    out
);

More realistic example: https://github.com/projf/projf-explore/blob/main/lib/maths/div_int.sv

[bluewww]

The second style is already supported on the master branch

[bjourne]

Can you tell me how to enable it? I've browsed through the docs and code but not found it out.

[gmlarumbe]

From 2adbba2 it should work by setting:

(setq verilog-indent-lists nil)

[bjourne]

Thanks it works.

[bjourne]

This setting unfortunately impacts other syntactic constructs than parameter lists negatively. F.e:

if (some_long_name * some_other_long_name &&
        something_here < something_else &&
        something_here < something_else &&
) begin
end

Here Emacs should lineup to the opening paranthesis.

Btw, I wonder if you guys know about SMIE? It has been developed by Stefan Monnier and is really good for creating consistent indentation for progmodes.

[gmlarumbe]

Hi @bjourne

The support for this indentation style was added recently and might still not cover all the use cases. I have made some changes that seem to work as you expect in b9a60cb. Can you test them and see if they work fine before merging into master?

Thanks!

[bjourne]

Sorry forgot to check. Will do it now.