Fix verilog-pretty-expr on declarations and update related tests

[gmlarumbe]

Hi,

This PR fixes the function verilog-pretty-expr when cursor is at a declaration.

It adds some cleaning to the verilog-indent-declaration, replacing some ifs without an else clause with (when condition ...) and indenting accordingly.

It also includes additional checks to set proper boundaries when looking for previous declaration as a template, as part of the process of the expression prettifying. Otherwise, declarations outside of a module port list get aligned with expressions inside module port lists, e.g:

module ExampOutputEvery (
                         /*AUTOOUTPUTEVERY*/
                         // Beginning of automatic outputs (every signal)
                         output o,
                         output tempa,
                         output tempb,
                         // End of automatics
                         input  i
                         );
   wire tempa = i;
   wire tempb = tempa;
   wire o     = tempb;
endmodule

This would be the result without the checks at verilog-indent-declaration after updating the declaration regexp:

module ExampOutputEvery (
                         /*AUTOOUTPUTEVERY*/
                         // Beginning of automatic outputs (every signal)
                         output o,
                         output tempa,
                         output tempb,
                         // End of automatics
                         input  i
                         );
    wire                        tempa = i;
    wire                        tempb = tempa;
    wire                        o     = tempb;
endmodule

Lastly, the 0test.el file is changed so that verilog-pretty-expr is run after verilog-pretty-declarations, since the latter removes spacing after the declaration, canceling the effect of verilog-pretty-expr.

The tests are updated and it seems to work fine.

Thanks!

[gmlarumbe]

Moved the 0test.el changes to #1781

This PR now only includes some boundaries checks to avoid mixing alignment between declarations inside and outside module port lists. I also added some logic to align only consecutive statements (e.g. in order to avoid alignment when there is an instance between declarations).

[acr4]

Hi @gmlarumbe , This commit introduced a warning that is emitted during native-compilation:

Warning (comp): verilog-mode.el:7681:15: Warning: Unused lexical variable `lim'

The result of save-excursion is stored to lim in the let varlist, but is no longer used in the body of the let.

[gmlarumbe]

Hi @acr4 ,

I added a fix in 922faeb. The warning should have disappeared.

Thanks!