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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Fix fontifying of variable names and overriding of keywords. #1787

Closed gmlarumbe closed 2 years ago

gmlarumbe commented 2 years ago

Hi,

This PR partially fixes issue #1752.

The changes in the updated regexp that @kaushalmodi proposed to detect signed/unsigned declarations were included after refactoring in 72c2b1f. However after this commit there was a bug in verilog-declaration-varname-matcher when trying to execute forward-sexp over a closing brace/bracket/parenthesis.

The PR also avoids fontify overriding of reserved keywords on variable declarations.

It still fontifies wrongly typedef enum declarations since these need some additional debugging (possibly in future PRs).

Thanks!

kaushalmodi commented 2 years ago

Thanks for working on this! I was unable to submit a proper PR after our last discussion in that issue thread.