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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Prevent verilog-pretty-expr from executing on multiline assignments #1791

Closed gmlarumbe closed 1 year ago

gmlarumbe commented 1 year ago

Hi,

This PR prevents the function verilog-pretty-expr from executing on multiline assignments.

In the example from previous PR #1790 the following snippet was wrongly aligned due to the presence of != in the multiline assignment:

      startc_c           <= (valid && (state == THE_START));
      end_c              <= (valid && (state == THE_END));
      valid_c            <= (valid &&
                  (state != IDLE) &&
                  (state != SKIP_DATA));

After the PR:

      startc_c <= (valid && (state == THE_START));
      end_c    <= (valid && (state == THE_END));
      valid_c  <= (valid &&
                   (state != IDLE) &&
                   (state != SKIP_DATA));

Thanks!