Add support to align expressions of continuous assignments

[gmlarumbe]

Hi,

This PR adds support to align expressions of continuous assignments. This is configured by the use of a variable (verilog-align-assign-expr) that is enabled by default.

Considering the following snippet:

   assign ExtraOut = 3'h0;
   assign SubOut = 3'h0;
   assign active_low_l = 4'h0;
   assign ignored_by_regexp = 4'h0;

Setting verilog-align-assign-expr to non-nil and running verilog-pretty-expr results in:

   assign ExtraOut          = 3'h0;
   assign SubOut            = 3'h0;
   assign active_low_l      = 4'h0;
   assign ignored_by_regexp = 4'h0;

The PR also adds a test to ensure that disabling the feature keeps backwards compatibility (tests/align_assign_expr_nil.sv).

Cheers!

[gmlarumbe]

I am not sure I understand your point. I believe that any other kind of alignment (declarations/expressions/comments) modifies many lines at once. Do you refer to the effect of verilog-auto-lineup when set to 'assignments or 'all?

I considered #1256 and the feature seemed a good idea but it would not be a problem at all if it was disabled by default. I can switch the new test file so that it tests alignment with the feature enabled and the rest are back to how they were before.

Would that be fine?

Cheers!