Handle line directives in port list while "parsing" AUTOINSTed modules

[berendo]

This PR attempts to fix and issue with line directives that may appear in the port list of an AUTOINSTed sub-module. Without this PR, the following top module:

module foo();

   bar i0 (
             /*AUTOINST*/
           );

endmodule // foo

instantiating this sub-module:

module bar(
`line 2 "bar.v" 0
           input  logic a
`line 3 "bar.v" 0
           );

endmodule // bar

results in:

module foo();

   bar i0 (
             /*AUTOINST*/
           // Inputs
           .a                           (a),
           .3                           (3),
           .0                           (0));

endmodule // foo

[wsnyder]

Thanks for your report & attempted fix. Adding it where you did this will ignore one token after the line which is incorrect, can you change it on aline to ignore to the end of line (next \n)? Or I can if you prefer. Also please put a test case into tests/autoinst_line.v and tests_ok/autoinst_line.v to check this.

[berendo]

Thanks @wsnyder. I’d be happy to improve the fix. Had to brush off my Lisp and page it in from tertiary storage, so I’ll probably tackle the more complete fix over the weekend.

I’m a long-time user and fan of your Verilog::Perl work, by the way, since the late 90s at Silicon Graphics. Thank you for all of your contributions... I’m amiss in not offering appreciation until this PR!

[berendo]

I’ll probably tackle the more complete fix over the weekend.

I think I covered your asks and updated the PR branch @wsnyder. Let me know how it looks!

[wsnyder]

Thanks, pushed.