search

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
247 stars 90 forks source link

Getting verilog-mode to print the originating module/port of the signal connected to an instance port #1802

Closed engrvns closed 1 year ago

engrvns commented 1 year ago

Hi verilog-mode team

Is there a way to have verilog-mode AUTO_TEMPLATE print the originating port/module of a signal connected to an input port. Notice the comments right next to the instance port below

Example:

module top (/AUTOARG/);

/ inst_module AUTO_TEMPLATE ( ...); / inst_module1 inst (/AUTOINST/);

inst_module2 inst (/AUTOINST/); endmodule

When expanded I would like to see -

inst_module inst ( .in1(in_port) //From port **.in2(in2_wire) //From inst_module2 <*** );

Thanks EVS

wsnyder commented 1 year ago

Not currently but you can hack similar behavior one time with an AUTO_TEMPLATE

/* Sub AUTO_TEMPLATE (
 .port3(@"vl-name"[] /*From @"vl-cell-type" @"vl-name"*/),
      );
    */
   Sub sub (/*AUTOINST*/
            .port3                      (port3 /*From Sub port3*/)); // Templated