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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Add support to align declarations/expressions within the region. #1806

Closed gmlarumbe closed 1 year ago

gmlarumbe commented 1 year ago

Hi,

This PR adds support for alignment of declarations and expressions within the marked region.

This is useful to fine-tune alignment of groups of declarations. For example:

module foo # (
    parameter int LONG_PARAMETER_NAME_DIM_1 = 8,
    parameter int LONG_PARAM_NAME_DIM_2 = 8,

    parameter integer EVEN_LONGER_PARAMETER_NAME_DIM_1 = 8,
    parameter integer EVEN_LONGER_PARAM_NAME_DIM_2 = 8
)(
    input logic in1,
    input logic [1:0] in2,

    output logic [LONG_PARAMETER_NAME_DIM_1-1:0][LONG_PARAM_NAME_DIM_2-1:0] o1,
    output logic [EVEN_LONGER_PARAMETER_NAME_DIM_1-1:0][EVEN_LONGER_PARAM_NAME_DIM_2-1:0] o2
);
endmodule

Without this support, running verilog-pretty-declarations and verilog-pretty-expr gives the following alignment:

module foo # (
    parameter int     LONG_PARAMETER_NAME_DIM_1        = 8,
    parameter int     LONG_PARAM_NAME_DIM_2            = 8,

    parameter integer EVEN_LONGER_PARAMETER_NAME_DIM_1 = 8,
    parameter integer EVEN_LONGER_PARAM_NAME_DIM_2     = 8
)(
    input logic                                                                           in1,
    input logic [1:0]                                                                     in2,

    output logic [LONG_PARAMETER_NAME_DIM_1-1:0][LONG_PARAM_NAME_DIM_2-1:0]               o1,
    output logic [EVEN_LONGER_PARAMETER_NAME_DIM_1-1:0][EVEN_LONGER_PARAM_NAME_DIM_2-1:0] o2
);
endmodule

After this PR, marking each paragraph independently and running verilog-pretty-declarations and verilog-pretty-expr results in:

module foo # (
    parameter int LONG_PARAMETER_NAME_DIM_1 = 8,
    parameter int LONG_PARAM_NAME_DIM_2     = 8,

    parameter integer EVEN_LONGER_PARAMETER_NAME_DIM_1 = 8,
    parameter integer EVEN_LONGER_PARAM_NAME_DIM_2     = 8
)(
    input logic       in1,
    input logic [1:0] in2,

    output logic [LONG_PARAMETER_NAME_DIM_1-1:0][LONG_PARAM_NAME_DIM_2-1:0]               o1,
    output logic [EVEN_LONGER_PARAMETER_NAME_DIM_1-1:0][EVEN_LONGER_PARAM_NAME_DIM_2-1:0] o2
);
endmodule

Thanks!