search

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
247 stars 90 forks source link

AUTOOUTPUTEVERY and AUTOWIRE creates duplicate definitions for signals #1812

Open engrvns opened 1 year ago

engrvns commented 1 year ago

Refer Last comment in - https://github.com/veripool/verilog-mode/issues/1811 The issue got closed and the comments could have been missed.

@wsnyder > I suspect you want AUTOOUTPUT instead. @user> But AUTOOUTPPUT does not promote a signal that's consumed internally as an output port and hardcoding them defeats the purpose. AUTOOUTPUTEVERY("regex") seems to be a perfect solution for this except duplicate definitions which seems to be a bug.

wsnyder commented 1 year ago

The problem here is AUTOOUTPUTEVERY is expanded after AUTOWIRE (and some others) which it needs to be as it wants to output what gets declared by AUTOWIRE (only if it is used but not if it isn't). But this bug wants the opposite order, that is do AUTOOUTPUTEVERY first, but then later do AUTOWIRE.

Obviously both orders can't be satisfied. So at this time I don't see how to implement this case correctly without some major rework I'm not ready to undertake.

wsnyder commented 1 year ago

Note the preexisting autooutputevery_wire.v test shows this exact case.