Fix bug in verilog-in-generate-region-p

[gmlarumbe]

Hi,

This PR fixes a bug in the function verilog-in-generate-region-p.

module foo;

    some_if my_if;

    // If point is here, `verilog-in-generate-region-p' returns t:
    //  - Wrongly detects the if of the interface type as if it was a
    //    keyword due to regexp word boundaries not set properly

    generate begin : test_gen
        if (CONDITION == "TRUE") begin

            always @(posedge Clk) begin
                if (!Rst_n) begin
                    signal <= 0;
                end else begin
                    signal <= 1;
                end
            end

        end else if (CONDITION == "FALSE") begin

            always @(posedge Clk) begin
                if (!Rst_n) begin
                    signal <= 0;
                end else begin
                    signal <= 2;
                end
            end

        end else begin

            always @(posedge Clk) begin
                if (!Rst_n) begin
                    signal <= 0;
                end else begin
                    signal <= 3;
                end
            end

        end
    end : test_gen

    endgenerate

    // If point is here, `verilog-in-generate-region-p' returns t:
    //  - Wrongly detects the if of always blocks as if they were part
    //    of the 'generate if' condition

endmodule

It includes two commits:

• First commit adds missing generate keywords in related tests and adds one for #1404, which seems to have been fixed already
• Second commit rewrites the function verilog-in-generate-region-p, delegating the complexity of nesting to verilog-forward-sexp

Thanks!