veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
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Interfaces from AUTOINST are not propagated as ports #1816

Open sarava49 opened 1 year ago

sarava49 commented 1 year ago

Hello,

My design uses interfaces for transmitting different complex types of signals. When using AUTOINST to instantiate a module into another one, the interfaces show up correctly at the instantiation code. However, these signals are not propagated as ports to the module that owns the instance, even though the non-interface-type signals coming from the same instance are properly created.

Is there any variable that has to be set in order to enable interfaces to be brought up the hierarchy?

I created a simple test code to show the issue. It is composed of 3 files: int_i.sv (interface declaration), lower.sv (module that will be instantiated at a higher level), and top.sv (the top level that instantiates the "lower" module).

int_i.sv

interface int_i

logic my_input;
logic my_output;

modport master (
  input  my_input,
  output my_output
);

modport slave (
  input  my_output,
  output my_input
);

endinterface

lower.sv

module lower (
    input         some_input,
    output        some_output,
    my_int.master my_int
);

assign my_int.my_output = some_input;
assign some_output = my_int.my_input;

endmodule

top.sv, BEFORE running verilog-mode

module top (
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);

lower u_lower
(/*AUTOINST*/);

endmodule

top.sv, AFTER running verilog-mode

module top (
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input                   some_input,             // To u_lower of lower.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output                  some_output             // From u_lower of lower.v
// End of automatics
);

lower u_lower
(/*AUTOINST*/
 // Interfaces
 .my_int                                (my_int.master),
 // Outputs
 .some_output                           (some_output),
 // Inputs
 .some_input                            (some_input));

endmodule

In this example, "my_int.master" was not brought up as ports to the "top" module.

Thank you for any tips,

Marcelo.

wsnyder commented 1 year ago

Interfaces are neither inputs nor outputs. There would need to be a new AUTOINTERFACE similar to AUTOINPUT/AUTOOUTPUT added.

Perhaps you'd be willing to contribute a pull request to implement it?

sarava49 commented 1 year ago

Thank you for the feedback. And for this amazing tool!

I'm not sure I'm capable of implementing it, as I'm not familiar with LISP, but I'll give it a try. It might take a while!