veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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What magic sauce is required to indent typedef's correctly? #1823

Open shareefj opened 1 year ago

shareefj commented 1 year ago

I'm struggling with indentation again and feel like I've been here before but haven't managed to find anything that works. All the examples and similar issues all point at using verilog-typedef-regexp but I haven't managed to get it to work yet. I do recall that on previous issues where this didn't work, I realised I had to set it in the child module for AUTO's to work, but in this case I've tried pretty much every permutation and it still fails.

As an example, how do I get my_special_t to be indented correctly?

package test_pkg;
  typedef enum logic
    {
     StateOne = 1'b0,
     StateTwo = 1'b1
     } my_special_t;
endpackage

module test
  import test_pkg::*;
  #(
    parameter int TestParam = 1
    )(
      input logic clk,
      input logic rst_n,
      input       my_special_t special
      );
endmodule

// Local Variables:
// verilog-library-directories:(".")
// verilog-typedef-regexp:"_t$"
// End:
wsnyder commented 1 year ago

There's also verilog-align-typedef-regexp, but it doesn't seem to help this. Another possibility (what I use) is

// verilog-auto-lineup: nil

Then manually delete indent once as this won't do it for you.

Fixes for this would be welcome.

gmlarumbe commented 1 year ago

Hi @shareefj ,

@wsnyder might help me out here, but I think that the variable verilog-typedef-regexp is only used for AUTOs.

For indentation/alignment you have two options:

If you want to also fontify/syntax highlight the typedefs set by previous two variables you can have a look at the verilog-ext package.