veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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2-d array and 1-d array indexing in AUTO_TEMPLATE #1826

Closed Grmarder closed 1 year ago

Grmarder commented 1 year ago

Is there a way to implement the example below : in AUTO_TEMPLATE there is ONE template for concatenation of signals which might be 1D or 2D arrays

module array_1d_2d 
(
input [0:1] [15:0] array_2d,
output [0:1] array_1d
);
endmodule

module top
();

/*array_1d_2d AUTO_TEMPLATE
(
array_.\(.*\) ({client[0]_\1[What to write here?],client[1]_\1[What to write here?]});
);
*/
array_1d_2d array_1d_2d_inst
(/*AUTOINST*/
.array_2d  ({client_2d[0][15:0],client_2d[1][15:0]}),
.array_2d  ({client_1d[0],client_1d[1]})
);
endmodule
wsnyder commented 1 year ago

You could write a complicated LISP formula to do this (see some of the "test" examples in githib), but unless you have a huge number of signals it's probably clear to not bother. Alternatively perhaps using a parameter to represent the "15" will make the code cleaner.