the define macro after the `ifdef, can't mask the /*AUTOINPUT*/ and the instance

[e665107]

Hi Look at the examle follow:

`ifdef ADDER4
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
adder4   adder4_inst(/*AUTOINST*/); // (vhdl not support yet)
`endif

The macro ADDER4 is undefined, but the autoinput will be expanded! And the adder4 will be detected!

If i want the right result, need write like this:

`ifdef ADDER4
///*AUTOINPUT*/
///*AUTOOUTPUT*/
///*AUTOREG*/
// adder4    adder4_inst(/*AUTOINST*/); // (vhdl not support yet)
`endif

Althouth the work is not very heavy， but it looks like some ugly! Dose this have a solution?

[wsnyder]

Verilog-mode does not support ifdefs: https://github.com/veripool/verilog-mode/blob/master/FAQ.rst#why-do-the-autos-ignore-my-ifdefs

there is no direct way to do this.