It there a way to align code inside assigns like follow?

[LeoGitHuber]

The default verilog-mode config works like follow.

   assign muldiv_state_nxt =
                            ({MULDIV_STATE_WIDTH{state_0th_exit_ena      }} & state_0th_nxt      )
     | ({MULDIV_STATE_WIDTH{state_exec_exit_ena     }} & state_exec_nxt     )
       | ({MULDIV_STATE_WIDTH{state_remd_chck_exit_ena}} & state_remd_chck_nxt)
         | ({MULDIV_STATE_WIDTH{state_quot_corr_exit_ena}} & state_quot_corr_nxt)
           | ({MULDIV_STATE_WIDTH{state_remd_corr_exit_ena}} & state_remd_corr_nxt)
             ;

what I want is

   assign muldiv_state_nxt =
             ({MULDIV_STATE_WIDTH{state_0th_exit_ena      }} & state_0th_nxt      )
            | ({MULDIV_STATE_WIDTH{state_exec_exit_ena     }} & state_exec_nxt     )
            | ({MULDIV_STATE_WIDTH{state_remd_chck_exit_ena}} & state_remd_chck_nxt)
            | ({MULDIV_STATE_WIDTH{state_quot_corr_exit_ena}} & state_quot_corr_nxt)
            | ({MULDIV_STATE_WIDTH{state_remd_corr_exit_ena}} & state_remd_corr_nxt)
            ;

I have tried to set several variable, but none of them work like above. Would you like to give me some suggestions?

[wsnyder]

I agree your formatting looks better, and that's how I personally like it too. To get that you need to change the Verilog code a bit, have = on a new line (so the lines are longer for continuations), and a ( to anchor the expressions:

   assign muldiv_state_nxt
     = (({MULDIV_STATE_WIDTH{state_0th_exit_ena      }} & state_0th_nxt      )
        | ({MULDIV_STATE_WIDTH{state_exec_exit_ena     }} & state_exec_nxt     )
        | ({MULDIV_STATE_WIDTH{state_remd_chck_exit_ena}} & state_remd_chck_nxt)
        | ({MULDIV_STATE_WIDTH{state_quot_corr_exit_ena}} & state_quot_corr_nxt)
        | ({MULDIV_STATE_WIDTH{state_remd_corr_exit_ena}} & state_remd_corr_nxt)
        );