Fix indention for restrict_property_statement

[pbing]

verilog-indent-buffer for restrict_property_statement leads to wrong indention:

module tb1;
   a: restrict property (1);
      b: assume property (1);
      c: assume property (1);
      endmodule

It should be:

module tb1;
   a: restrict property (1);
   b: assume property (1);
   c: assume property (1);
endmodule

verilog-mode version 2023-06-06-86c6984-vpo-GNU

[wsnyder]

Perhaps you could contribute a pull request to fix this?

[acr4]

See PR #1838 for a proposed solution.

[kzhang70]

The fix does NOT work if property is not in the same line as the label.

module tb1; a: restrict property (1); b: assume property (1); c: assume property (1); endmodule