veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Fix indention for cover_sequence_statement #1837

Closed pbing closed 1 year ago

pbing commented 1 year ago

verilog-indent-buffer for cover_sequence_statement leads to wrong indention:

module tb2;
   a: cover sequence (1);
      b: cover property (1);
      c: cover property (1);
      endmodule

It should be:

module tb2;
   a: cover sequence (1);
   b: cover property (1);
   c: cover property (1);
endmodule

verilog-mode version 2023-06-06-86c6984-vpo-GNU

wsnyder commented 1 year ago

Perhaps you could contribute a pull request to fix this? (And #1836 likely similar area to fix.)

acr4 commented 1 year ago

See PR #1838 for a proposed solution.