verilog-mode.el (verilog-property-re, verilog-beg-of-statement, verilog-calc-1): Concurrent SVA statement pattern-matching learns 'restrict property' and 'cover sequence' expression for proper indentation around those constructs. This addresses more patterns in IEEE 1800-2017's 'concurrent_sasertion_statement' grammar.
tests{,_ok}/indent_assert_property.v: Add test cases from GitHub user 'pbing'
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verilog-mode.el (verilog-property-re, verilog-beg-of-statement, verilog-calc-1): Concurrent SVA statement pattern-matching learns 'restrict property' and 'cover sequence' expression for proper indentation around those constructs. This addresses more patterns in IEEE 1800-2017's 'concurrent_sasertion_statement' grammar.
tests{,_ok}/indent_assert_property.v: Add test cases from GitHub user 'pbing'
We appreciate your contributing to Verilog-Mode.
By contributing you agree this code will be licensed under the GNU Public License.
Please check your github name is set to your real name (click on your avatar icon in upper right, then "settings" then "Name".) This should match your system's ~/.gitconfig user name.