Remove the modport of the interface from AUTOINST

[szkarn]

Hi, i wonder how to remove or do not generate the modport of the interface when using AUTOINST

like removing the [.master] of [.svi_modport (svi_modport.master),] in below codes:

interface svi;
   logic       enable;
   modport master (input enable);
endinterface

module InstModule
  (input      clk,
   svi.master svi_modport,
   svi        svi_nomodport);
endmodule

module top;
   InstModule instName
     (/*AUTOINST*/
      // Interfaces
      .svi_modport         (svi_modport.master),
      .svi_nomodport       (svi_nomodport),
      // Inputs
      .clk                 (clk));
endmodule

I want to obtain this：

module top;
   InstModule instName
     (/*AUTOINST*/
      // Interfaces
      .svi_modport         (svi_modport),
      .svi_nomodport       (svi_nomodport),
      // Inputs
      .clk                 (clk));
endmodule

thanks for answer or any tips

[wsnyder]

Add it yourself before the AUTOINST.

module top;
   InstModule instName
     (
      // Interfaces
      .svi_modport         (svi_modport),
      /*AUTOINST*/
      // Interfaces
      .svi_nomodport       (svi_nomodport),
      // Inputs
      .clk                 (clk));
endmodule

[szkarn]

Thanks, Snyder. But the interfaces with modport is majority ports for intance in my code, not minority. It's inconvenient to do it manually. In my work, the interface is used to connected with other submodule with same interface name, which does not need the modport. In other words, the [.master] and [.slave] are inconsistent. I wonder why the connected interface must have the modport after AUTOINST, and whether it is used in the verification scheme. I appreciate it if you can give me some suggestions. Can the modport of interface to be configurable?

[wsnyder]

If you have a modport in the cell you are instancing it should also be where it's instantiated, it's better for readability. It's also strange if you are using modports for one module but not another, that's legal, just unusual. I'm still not understanding what is breaking for you with what verilog-mode does by including the modport, you talk about it affecting another usage but that's not shown and would be a different instance that should still properly connect using AUTOs.

[szkarn]

Thanks for your response. An example shown below:

interface svi;
   logic       enable;
   modport master (input enable);
   modport slave (output enable);
endinterface

module MasterModule
  (input      clk,
   svi.master svi_modport);
endmodule

module SlaveModule
  (input      clk,
   svi.slave svi_modport);
endmodule

module top;
   ...
   InstModule MasterModule
     (/*AUTOINST*/
      // Interfaces
      .svi_modport         (svi_modport.master),
      // Inputs
      .clk                 (clk));
   InstModule SlaveModule
     (/*AUTOINST*/
      // Interfaces
      .svi_modport         (svi_modport.slave),
      // Inputs
      .clk                 (clk));
endmodule

it seems like I need an extra assign svi_modport.master = svi_modport.slave, which would not generated by "AUTO". cause I'm not familiar with systemverilog, could you give me some suggestions about it?

[wsnyder]

You need to instantiate the interface in the upper module. Then it can connect as svi_modport, svi_modport.master, or svi_modport.slave.

module t;
   svi svi_modport;
   InstModule instName
     (/*AUTOINST*/
      // Interfaces
      .svi_modport                      (svi_modport.master));
endmodule