Typedef struct signals can't be AUTOINPUT(AUTOOUTPUT) generated when AUTOINST

[lucychole]

Hi Wilson Snyder

The following are pkg modules, submodules and topmodules, when using "AUTOINST" automatic instantiation, the integration is fine, but when "AUTOOUTPUT" and "AUTOINPUT", the signals of the package type cannot be automatically defined, how do you need to set it?

package simet_pkg；
import simet_define.sv ：：*；

typedef struct packed{
logic [2:0]         mastered;
slice_resp_t        resperr;
…

}slv_req_flit_t;

typedef struct packed{
logic [2:0]         mastered;
slice_tagop_t   tagop;
…

}slv_rsp_flit_t;

endpackage : tibet_slice_pkg

module submodule;
input                   slv_slice_req_valid0;
input                   slv_slice_req_valid1;
output                  slv_slice_req_credit;

input   slv_reg_flit_t          slv_slice_req_payload0;
output  slv_resp_flit_t             slv_slice_rsp_payload0;
logic…
endmodule

module top(
/*AUTOINPUT*/
slv_slice_req_valid0;
slv_slice_req_valid1;

/*AUTOOUTPUT*/
slv_slice_req_credit
);

Submodule（/*AUTOINSTANCE*/）
U_instance(
.slv_slice_req_valid0   (slv_slice_req_valid0)，
.slv_slice_req_valid1   (slv_slice_req_valid1)，
.slv_slice_req_credit   (slv_slice_req_credit)，
.slv_slice_req_payload0 (slv_slice_req_payload0)，
.slv_slice_rsp_payload0 (slv_slice_rsp_payload0)
）；
endmodule

As shown in the example above, the signal _slv_slice_reqpayload0 and _slv_slice_rsppayload0 are of type tpyedef, but the I/O interface cannot be automatically generated when instantiated automatically

[wsnyder]

https://github.com/veripool/verilog-mode/blob/master/FAQ.rst#why-do-the-autos-treat-systemverilog-types-as-signals