Open richyliu opened 5 months ago
Good debugging! Perhaps you could propose a patch to fix this - maybe just short circuit when called recursively?
I'm not that familiar personally with the indentation side of Verilog-Mode, so don't have suggestions as to the best approach.
In the following file, inserting a line before the last line is extremely slow
Adding more
a {
and}
in the above pattern increases the delay exponentially (or at least worst than linearly). The above is a minimally reproducible example. The following is an example of this issue in real SystemVerilog:The following is the profiler results: