Port alignment issues

[ramyamohandoss]

module csr (
    /*AUTOOUTPUT("^csr_")*/    
    output logic        csr_arready,            
    output logic        csr_awready,         
    output logic [RESP_WIDTH-1:0] csr_bresp,
    output logic        csr_bvalid,            
    output logic [CSR_DATA_WIDTH-1:0] csr_rdata,
    output logic [CSR_RESP_WIDTH-1:0] csr_rresp,
    output logic        csr_rvalid,             
    output logic        csr_wready,             

);

endmodule

There is no alignment between the columns where parameter is specified versus signal column. What can I do to fix this? Its true for both 1D and 2D array.

I want the expansion to look something like this

module csr (
    /*AUTOOUTPUT("^csr_")*/    
    output logic                                            csr_arready,            
    output logic                                            csr_awready,         
    output logic [RESP_WIDTH-1:0]           csr_bresp,
    output logic                                            csr_bvalid,            
    output logic [CSR_DATA_WIDTH-1:0] csr_rdata,
    output logic [CSR_RESP_WIDTH-1:0] csr_rresp,
    output logic                                           csr_rvalid,             
    output logic                                           csr_wready,             

);

Thanks

[wsnyder]

When I have (setq verilog-auto-lineup 'declarations) and reindent the section with C-c = it seems correct.

Note the explicit reindent is required, see the description in verilog-auto-lineup.