add AUTOLOCAL

[TerrenceSun]

This is another way of applying ignore to outputs. We can ignore output ports by adding it to verilog-auto-output-ignore-regexp，but it takes time when there are many ports to ignore. So, mark any output port by putting AUTOLOCAL in template, with this patch that port signal would be put into /AUTOWIRE/. This operation is only meaningful for output port, as use user defined singal as input is working fine.

I find the method useful and convenient, so just pull it for further discussion.

[wsnyder]

Is there a reason why verilog-auto-ignore-concat doesn't work for you instead?

[TerrenceSun]

The requirement comes from How do I remove outputs from AUTOOUTPUT?, but many user complain that these 4 methods are not very user friendly, especially for new users. As it is a two-step way of doing things, and user need to setup both AUTO_TEMPLATE and ignore list. It takes more effort to make it work and keep it synchronized cross design updates.

verilog-auto-ignore-concat only ignores concat style of ports connection, which cannot cover the generic way of using.

AUTOLOCAL is a one-step inline way, which can put the port into 'output ignore' list in AUTO_TEMPLATE.

I am also considering make this inline directive way more powerful as below:

1. AUTONOHOOKUP, for all kinds of port, only make the connection without wire/output/input.
2. AUTOLOCAL, for output port, make the connection and add it to AUTOWIRE list.
3. AUTOFORCEOUTPUT, for output port, make the connection and always add it to AUTOOUTPUT list.

More words about the last two use case. For AUTOLOCAL, it helps when user want to use the signals locally, for example, make simple modification of the value then feed it to input of another module. For AUTOFORCEOUTPUT, it helps when user also want to expose the port even it is the input of any other module. This helps more when the signal name is a pragmatically generated name.

[wsnyder]

verilog-auto-ignore-concat only ignores concat style of ports connection, which cannot cover the generic way of using.

The purpose is you use concats around what to ignore, using your example:

   /* a2 AUTO_TEMPLATE (
    .i1(i1),
    .o1({o1}),
    ) */

Why doesn't that work?

[TerrenceSun]

verilog-auto-ignore-concat only ignores concat style of ports connection, which cannot cover the generic way of using.

The purpose is you use concats around what to ignore, using your example:

   /* a2 AUTO_TEMPLATE (
    .i1(i1),
    .o1({o1}),
    ) */

Why doesn't that work?

I see. However is it possible to set verilog-auto-ignore-concat bias on each port? We currently use it as a file level global parameter.

[wsnyder]

However is it possible to set verilog-auto-ignore-concat bias on each port?

No, concats in ports are rare so the assumption is you aren't using concats in the AUTO port expressions.