instance ports order is not as delclaration order after set verilog-auto-inst-sort as nil

After I set the verilog-auto-ins-sort as nil, there is still the order style of input/output groupping. I want to have the original declaration order when I AUTOINST. How could I achieve it.

my variables setting:

// Local Variables:
// verilog-auto-inst-param-value: t
// verilog-library-directories:("")
// verilog-library-files:("")
// verilog-library-flags:("-f vlogfile_flat.f")
// verilog-auto-arg-sort: nil
// verilog-auto-inst-sort: nil
// verilog-auto-arg-sort: nil
// verilog-library-extensions:(".v" ".sv" ".vh")
// End:

The module deifne

module timesync_parity_dec_wrap #(
// parameter
    parameter PARITY_TYPE  = 0,     // parity type: 0--even parity, 1--odd parity
    parameter PARITY_CHUNK = 8,     // parity chunk, can be 8/16/32
    parameter DATA_WIDTH   = 32,
    parameter PARITY_WIDTH = ((DATA_WIDTH%PARITY_CHUNK) == 0) ? (DATA_WIDTH/PARITY_CHUNK) : (DATA_WIDTH/PARITY_CHUNK +1)    

)(
// user interface
    input                                       clk,
    input                                       rst_n,
    input       [DATA_WIDTH-1:0]                din,
    input                                       err_inj,        // error injection test
    input                                       err_clr,
    input       [PARITY_WIDTH-1:0]              din_parity,

    output      [DATA_WIDTH-1:0]                dout,
    output reg                                  err_parity    
);

The code after AUTO-INST

    /*timesync_parity_dec_wrap AUTO_TEMPLATE (
        .xxx                                        (xxx),
    );*/
    timesync_parity_dec_wrap #(/*AUTOINSTPARAM*/
        // Parameters
        .PARITY_TYPE                                (PARITY_TYPE),
        .PARITY_CHUNK                               (PARITY_CHUNK),
        .DATA_WIDTH                                 (DATA_WIDTH),
        .PARITY_WIDTH                               (PARITY_WIDTH))
    u_test_1(/*AUTOINST*/
        // Outputs
        .dout                                       (dout[DATA_WIDTH-1:0]),
        .err_parity                                 (err_parity),
        // Inputs
        .clk                                        (clk),
        .rst_n                                      (rst_n),
        .din                                        (din[DATA_WIDTH-1:0]),
        .err_inj                                    (err_inj),
        .err_clr                                    (err_clr),
        .din_parity                                 (din_parity[PARITY_WIDTH-1:0]));

The order style I want:

    /*timesync_parity_dec_wrap AUTO_TEMPLATE (
        .xxx                                        (xxx),
    );*/
    timesync_parity_dec_wrap #(/*AUTOINSTPARAM*/
        // Parameters
        .PARITY_TYPE                                (PARITY_TYPE),
        .PARITY_CHUNK                               (PARITY_CHUNK),
        .DATA_WIDTH                                 (DATA_WIDTH),
        .PARITY_WIDTH                               (PARITY_WIDTH))
    u_test_1(/*AUTOINST*/
        .clk                                        (clk),
        .rst_n                                      (rst_n),
        .din                                        (din[DATA_WIDTH-1:0]),
        .err_inj                                    (err_inj),
        .err_clr                                    (err_clr),
        .din_parity                                 (din_parity[PARITY_WIDTH-1:0]));
        .dout                                       (dout[DATA_WIDTH-1:0]),
        .err_parity                                 (err_parity),

veripool / verilog-mode

instance ports order is not as delclaration order after set verilog-auto-inst-sort as nil #1880