search

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
253 stars 90 forks source link

Skip over base-64-encoded protected data while reading declarations #19

Closed berendo closed 4 years ago

berendo commented 4 years ago

This PR attempts to fix Scan error: "Unbalanced parentheses", ... (and other) scanning errors that occur while verilog-mode reads module declarations for auto-instantiation of modules that contain Base64-encoded lines for protected Verilog.

I am not able to provide a test case at this time as we encountered this issue in a licensed 3rd-party IP block.

wsnyder commented 4 years ago

Thanks for the patch.

I think this needs to be moved under the /* check, otherwise if it's commented out it won't work right. Can you try that please?

Also can you look at the case that breaks and handcraft a similar test? I suspect from your error you just need a module, a /AUTOARG/ then the `pragma with some following lines with a paren, and the end pragma.

berendo commented 4 years ago

Also can you look at the case that breaks and handcraft a similar test?

@wsnyder take a look at the fresh force-pushed state of the PR - I've hand-crafted a test case and also moved the block of code under the /* case as you suggested.

wsnyder commented 4 years ago

Thanks for your work & adding the test, pushed here and to Emacs trunk.