Indenting of user-defined data types

[veripoolbot]

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Author Name: David Rogoff Original Redmine Issue: 386 from https://www.veripool.org

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Hi again. I've got a ton of signals and ports that are various typedefs/structs. When verilog-mode indents these, it doesn't recognize the types and doesn't indent them properly. For example:

typedef  logic [7:0] mytype1_s;  // cell pointer

typedef struct packed {
    mytype1_s aa;
    celloffset_s bb;
    logic       cc;
    logic       dd;
    logic       ee;
    } mystruct1_s;

module test_indent
     (
      input logic         clock,
      output logic [31:0] data_out,
      input               mystruct1_s p1, // NOT INDENTED CORRECTLY
      output              to_qram_rdarb_s [3:0] out_arry1, // NOT INDENTED CORRECTLY

      output logic        done
      );

endmodule // test_indent
// Local Variables:
// verilog-typedef-regexp: "_s$" 
// End:

Is there some way to let verilog-mode know about my data types? Something like what verilog-typedef-regexp does for AUTOs?

Thanks!

David

ps - I originally filed this in the forum instead of as an issue:

http://www.veripool.org/boards/14/topics/show/562

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2012-02-05T02:32:13Z

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I searched for "int" in verilog-mode.el and followed verilog-declaration-core-re to verilog-declaration-re. Adding to verilog-declaration-re will probably do what you want; I'd add it via a new variable that gets merged into declaration-re. However note it will be global and needs to be correct before verilog-mode is compiled as these variables are defconst for speed, which is nasty.

Optimally, as you requested it would use verilog-typedef-regexp. However to do so properly, since verilog-typedef-regexp can be different per buffer (buffer-local) verilog-declaration-re and all of the variables downstream that are now constant need to be recomputed on each buffer and made buffer-local. That's very ugly. Instead it's probably better that those variables become defsubst's so they evaluate instead when used. I'm not sure how much slower this will make indentation.

Ditto adding it to verilog-font-lock-keywords, though that's at least a normal variable.

I think you see why this hasn't been done yet.

If you'd like to take a stab at this, and get something reasonably clean out, I'll take the patches back.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2012-02-05T02:35:28Z

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BTW verilog-typedef-regexp if used needs to be specified as "\w+_s\>" or similar, since it needs to match in the middle of a line instead of only against a string with one variable in it.

[veripoolbot]

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Original Redmine Comment Author Name: David Rogoff Original Date: 2012-02-06T01:08:55Z

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Ack. Doesn't look good. The first approach - having to set variables before gererating the .elc file doesn't seem like it would work. The 2nd approach, using verilog-typedef-regexp, is how it would need to work to be useful. It should be buffer local. I'm not up on defsubst, so I can't comment.

As for verilog-font-lock-keywords, I think it needs to be a separate variable/face just for user-defined types. I want to be able to tell LRM keywords from stuff I add.

I don't really have time or knowledge to work on this, but I'll probably try anyway :)

[veripoolbot]

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Original Redmine Comment Author Name: David Rogoff Original Date: 2019-07-23T01:05:59Z

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Hi Wilson.

I'm hitting this again and my elisp still isn't good enough to fix this correctly. However, I've hacked a solution for my own use. I've edited my local copy of verilog-mode.el to manually add the handful of user-defined types and it seems to work - at least for highlighting and indenting.

I added these lines in the middle of defconst verilog-declaration-core-re (around line 2750):

    ;; my types
    "uint_t" "wreal4state"

And these around 3180:

    (verilog-my-keywords
     (eval-when-compile
       (verilog-regexp-opt
        '("wreal4state" "uint_t") nil)))

And these in setq verilog-fint-lock-keywords around line 3270:

      (cons (concat "\\<\\(" verilog-my-keywords "\\)\\>")
            'font-lock-type-face)

It's a hack but pretty manageable - at least until it breaks something. Maybe this will give you an idea on a better version using a variable / regex in the Local Variables section.

David