End mis-indents with sized replication

[veripoolbot]

---

Author Name: Wilson Snyder (@wsnyder) Original Redmine Issue: 955 from https://www.veripool.org

---

Reported via email from Alessandro Contreras-Grassi alcontre@terpmail.umd.edu

Please follow up by CCing him.

Expected behavior: "end" is indented correctly with "if" What happens: the "end" is indented to match with "always", when using the parameter 's' in {s{1'b0}}. If I use the numeric value instead, it indents correcty.

== The code: ==

module test (input a, input b, output c);
        parameter s = 4;
        reg [s:0] myreg;
        always @(posedge a) begin
               if (b) begin
                  r <= {s{1'b0}};
               end // <-- this end will be improperly indented unless
's' is replaced with e.g. 4
        end
end

Emacs : GNU Emacs 24.5.1 (x86_64-apple-darwin14.3.0, NS apple-appkit-1347.57) of 2015-05-27 on alex-mbp.local Package: verilog-mode v2015-06-26-832636e-vpo

(setq
 verilog-active-low-regexp nil
 verilog-after-save-font-hook nil
 verilog-align-ifelse nil
 verilog-assignment-delay ""
 verilog-auto-arg-sort nil
 verilog-auto-declare-nettype nil
 verilog-auto-delete-trailing-whitespace nil
 verilog-auto-endcomments t
 verilog-auto-hook nil
 verilog-auto-ignore-concat nil
 verilog-auto-indent-on-newline t
 verilog-auto-inout-ignore-regexp nil
 verilog-auto-input-ignore-regexp nil
 verilog-auto-inst-column 40
 verilog-auto-inst-dot-name nil
 verilog-auto-inst-interfaced-ports nil
 verilog-auto-inst-param-value nil
 verilog-auto-inst-sort nil
 verilog-auto-inst-template-numbers nil
 verilog-auto-inst-vector t
 verilog-auto-lineup 'declarations
 verilog-auto-newline nil
 verilog-auto-output-ignore-regexp nil
 verilog-auto-read-includes nil
 verilog-auto-reset-blocking-in-non t
 verilog-auto-reset-widths t
 verilog-auto-save-policy nil
 verilog-auto-sense-defines-constant nil
 verilog-auto-sense-include-inputs nil
 verilog-auto-star-expand t
 verilog-auto-star-save nil
 verilog-auto-template-warn-unused nil
 verilog-auto-tieoff-declaration "wire"
 verilog-auto-tieoff-ignore-regexp nil
 verilog-auto-unused-ignore-regexp nil
 verilog-auto-wire-type nil
 verilog-before-auto-hook nil
 verilog-before-delete-auto-hook nil
 verilog-before-getopt-flags-hook nil
 verilog-before-save-font-hook nil
 verilog-cache-enabled t
 verilog-case-fold t
 verilog-case-indent 2
 verilog-cexp-indent 2
 verilog-compiler "echo 'No verilog-compiler set, see \"M-x
describe-variable verilog-compiler\"'"
 verilog-coverage "echo 'No verilog-coverage set, see \"M-x
describe-variable verilog-coverage\"'"
 verilog-delete-auto-hook nil
 verilog-getopt-flags-hook nil
 verilog-highlight-grouping-keywords nil
 verilog-highlight-includes t
 verilog-highlight-modules nil
 verilog-highlight-p1800-keywords nil
 verilog-highlight-translate-off nil
 verilog-indent-begin-after-if t
 verilog-indent-declaration-macros nil
 verilog-indent-level 3
 verilog-indent-level-behavioral 3
 verilog-indent-level-declaration 3
 verilog-indent-level-directive 1
 verilog-indent-level-module 3
 verilog-indent-lists t
 verilog-library-directories '(".")
 verilog-library-extensions '(".v" ".sv")
 verilog-library-files nil
 verilog-library-flags '("")
 verilog-linter "echo 'No verilog-linter set, see \"M-x
describe-variable verilog-linter\"'"
 verilog-minimum-comment-distance 10
 verilog-mode-hook 'verilog-set-compile-command
 verilog-mode-release-emacs nil
 verilog-mode-version "2015-06-26-832636e-vpo"
 verilog-preprocessor "vppreproc __FLAGS__ __FILE__"
 verilog-simulator "echo 'No verilog-simulator set, see \"M-x
describe-variable verilog-simulator\"'"
 verilog-tab-always-indent t
 verilog-tab-to-comment nil
 verilog-typedef-regexp nil
 verilog-warn-fatal nil
 )

[veripoolbot]

---

Original Redmine Comment Author Name: Alex Reed Original Date: 2015-08-12T12:40:34Z

---

ACK. I won't be able to look at this for a couple days at least, but I don't think it's a terribly difficult fix.

[veripoolbot]

---

Original Redmine Comment Author Name: Alex Reed Original Date: 2018-03-26T20:48:30Z

---

Yeah, I see this too. Unfortunately, I'm not in a great place to dig in to this (again) in the near term, due to looming tape-out schedules. Some of the indentation code is getting untenable (and I'm probably to blame for some of it!). Parsing a grammar as complex as Verilog/SystemVerilog with regexes is pretty ugly.

Whenever I've looked at this, it becomes a slippery slope. Anything that resolves to an elaboration-time constant should be legal for the replication value. That includes $system() functions, user functions/tasks, fancy macro magic, and other arbitrarily complex statements. Nested {} blocks can be found in multi-dimensional arrays, replication statements, and constraint blocks. Figuring out which is which always ends up breaking one of the other parsers, or killing performance.

The current behavior is definitely wrong, but I don't know how to fix it.