Restart alignment after empty or comments lines - Githubissues

Author Name: Enzo Chi Original Redmine Issue: 960 from https://www.veripool.org

Currently the verilog-mode would try to align the signal name in the declaration with the port name as below:

     module img_cnt(
                    logic clk,
                    logic rst,
                    logic frame_vld,
                    logic line_vld,
                    logic data_vld
                    );

        // Expect to restart the alignment from here
        int unsigned      frame_cnt = 0;
        int unsigned      line_cnt = 0;
        int unsigned      data_cnt = 0;

But I think the declaration should has its own alignment (aligned '=' as bonus).

     module img_cnt(
                    logic clk,
                    logic rst,
                    logic frame_vld,
                    logic line_vld,
                    logic data_vld
                    );

        // Expect to restart the alignment from here
        int unsigned frame_cnt = 0;
        int unsigned line_cnt  = 0;
        int unsigned data_cnt  = 0;

So is it possible to add some variables to control restart the alignment after empty lines or comment lines?

veripool / verilog-mode

Restart alignment after empty or comments lines #960