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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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Do not overwrite existing assignments in new_contassign(). #1049

Closed veripoolbot closed 8 years ago

veripoolbot commented 8 years ago

Author Name: Stefan Tauner (@stefanct) Original Redmine Issue: 1049 from https://www.veripool.org Original Date: 2016-03-18

See attachment

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Stefan Tauner (@stefanct) Original Date: 2016-03-18T15:44:38Z

Oh, and you probably want to do the same to new_defparam(), possibly new_cell() and maybe even others. I did not check anything besides new_contassign().

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2016-03-20T14:43:52Z

Fixed in git towards 3.419. Thanks for the patch, though I did it a bit differently as was worried having a retry loop has a risk of performance problems.

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Stefan Tauner (@stefanct) Original Date: 2016-03-23T19:10:59Z

I noticed that you often go that way (i.e. adding fields when other solutions exist) in Verilog-Perl. Have you ever benchmarked those approaches? My understanding of current architectures is that memory latency eats up pretty many optimizations using in-application caching. Verilog-Perl already has a quite huge memory footprint already and adding more fields for things that are in very few cases used at all (Since when was this particular case broken? Did it ever work?) does not help with that.

Anyway, any fix in this case is welcomed so thanks a lot for that! I hope to be able to work on upstreaming the vector patch soon-ish (but I do so since December so... ;)

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2016-07-30T14:05:04Z

In 3.420.