Question: Couldn't Merge (port) -> how to solve - Githubissues

veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

https://www.veripool.org/verilog-perl

Artistic License 2.0

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Question: Couldn't Merge (port) -> how to solve #1066

Closed veripoolbot closed 8 years ago

veripoolbot commented 8 years ago

Author Name: John John John Original Redmine Message: 1984 from https://www.veripool.org

Hello,

I'm receiving the "Couldn't Merge" message on the AUTOREGINPUT - why? How to solve? Why happens? What exactly "couldn't Merge"?

Thank you!

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2016-09-06T11:34:17Z

It means you have two (or more) instances creating an output e.g. "output [1] example" and "output [6] example", and when verilog-mode makes a AUTOWIRE for "example" it can't make a declaration e.g. "wire [1,6] example" is not legal or not easy to figure out. Manually declare the wire.