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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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Question: an AUTO to propagate interface to top level port #1090

Closed veripoolbot closed 8 years ago

veripoolbot commented 8 years ago

Author Name: Dominique Chen Original Redmine Message: 2053 from https://www.veripool.org

Hi,

I search around but didn't get a concrete answer. Is there an AUTOINTERFACE similar to an AUTOINPUT that will automatically propagate interface connections from a lower level module instantiated with AUTOINST ?

Thanks.

Dominique

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2016-10-28T18:17:20Z

Normal AUTOINST will probably do what your asking, if not attach an example of what you want to happen.

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Dominique Chen Original Date: 2016-10-28T18:36:02Z

At the module instantiation, I have

sensor_slice slice0 (/AUTOINST/ // Interfaces .sense_0 (sensor0_slice0), // Templated .sense_1 (sensor1_slice0), // Templated .sense_2 (sensor2_slice0), // Templated .....

Inside module sensor_slice, I have module sensor_slice ( sensor_afe_if sense_0 , sensor_afe_if sense_1 , sensor_afe_if sense_2 ,

where sensor_afe_if is the name of the interface.

At the top level where sensor_slice is instantiated, I'd like to see

module top ( sensor_afe_if sensor0_slice0, sensor_afe_if sensor1_slice0, sensor_afe_if sensor2_slice0, ... );

What am I missing ?

Thank you.

Dominique